1. Field of the Invention
The present invention relates generally to configurations of semiconductor memory devices and particularly to those controlling a timing of an operation thereof.
2. Description of the Background Art
Dynamic random access memory (DRAM) and other similar semiconductor memory devices have been improved to operate more rapidly for example to access data in a short period of time as the system used, such as a personal computer, has been improved to operate more rapidly.
For example, a semiconductor memory device has been put to practical use to provide an increased operating speed. It is a so-called synchronous semiconductor memory device, such as synchronous dynamic random access memory (SDRAM), operating in synchronization with an externally applied clock signal.
For such a synchronous semiconductor memory device, for example in a plurality of semiconductor memory devices incorporated on a board a signal can be read or taken in in response to a clock. Thus an effect for example of a skew of a signal can be alleviated to achieve a rapid operation.
Meanwhile in recent years semiconductor memory devices are increasingly applied for example to a so-called xe2x80x9cpalm devicexe2x80x9d and other similar mobile terminals. Such mobile terminals, operating on a battery, are required to operate with small power consumption, as well as operate rapidly.
As such, if a semiconductor memory device manufactured to correspond to a system of a rapid operation, as described above, is used for example in a mobile terminal, it does not necessarily operate at high frequencies.
If the semiconductor memory device has a specification to operate in synchronization with an external clock signal to accommodate such a rapid operation as described above and the clock signal reduces in frequency, the device""s access time or the like can be unnecessarily reduced.
Hereinafter this disadvantage will be described more specifically.
FIG. 17 is timing plots for illustrating a read operation in a conventional synchronous semiconductor memory device.
At a time t1 the semiconductor memory device receives a read command DR for the sake of illustration.
If the device is a synchronous semiconductor memory device accommodating a rapid operation it starts outputting data through data input/output terminal DA at a time to, or two clocks after the read command is applied with a clock signal CLK transitions from low to high. Such a time elapsing after read command DR is applied and before read data is output externally from a semiconductor memory device, is referred to as a xe2x80x9cCAS latency (CLK).xe2x80x9d For example, data is output two clocks after for a CAS latency of two.
Furthermore, such a CAS latency can be set to have a different value depending on a designation provided by a combination of control signals externally applied to a semiconductor memory device, or a mode register set. For example, FIG. 17 also represents a timing of outputting data for a CAS latency of three. In this example, when read command DR is applied and a three clocks then elapses and a time TM3 is thus arrived at, read data is output from the semiconductor memory device.
If when read command DR is applied and a predetermined number of clocks then elapses before read data is read out, the data is read in the following operation:
More specifically, applying read command DR is preceded by selecting a row in a memory cell array and starting reading data from a plurality of memory cells of the selected row, and a temporal period corresponding to a CAS latency can be afforded before read command DR triggers an operation related to a column of the semiconductor memory device, i.e., before an operation is started to read the data of the read row that corresponds to a selected column of the memory cell array and output the data externally from the semiconductor memory device.
Thus if a clock frequency is high, the device can output data in synchronization with the clock signal CLK.
Such a CAS latency is defined to be a number of clocks in accordance with a rapid clock frequency operation when it is designed.
FIG. 18 represents an operation in waveform of such a synchronous semiconductor memory device when it is operated in synchronization with a slower clock signal CLK.
As has been described previously, at time t1 when clock signal CLK transitions from low to high, read command DR is applied. For a CAS latency of two or three, the devise outputs data when time t1 is followed by two or three clocks and time TM3 or to is thus arrived at.
If clock signal CLK has a low frequency, the device does not require the CAS latency of two and it can output read data for which a column related operation is started at time t1, for example before time t1 is followed by one clock and time to is thus arrived at. Thus, if the device operates in synchronization with clock signal CLK of such a low frequency, it can externally output read data for example with a CAS latency of one or one clock after read command RD.
Thus if the device is assumed to be used in a system such as a mobile terminal, it is required to be capable of operation with the CAS latency of one which is not assumed in a rapid operation.
However, if a semiconductor memory device operable conventionally with a CAS latency of two or three is simply provided with a circuit in a different system to control a timing and it is thus also operable with the CAS latency of one, it would have a disadvantageously increased circuit area.
The present invention contemplates a semiconductor memory device operable with both a CAS latency of one and that of more than one and having a timing control configuration preventing the device from further increasing in circuit area.
The present invention generally provides a semiconductor memory device synchronized with an external clock signal to input a command and input and output data, including: a control circuit controlling an operation of the semiconductor memory device; a memory cell array including a plurality of memory cells arranged in rows and columns; an internal clock circuit operative in response to the external clock signal to generate an internal clock signal; a clock signal line transmitting the internal clock signal; a clock conversion circuit receiving the internal clock signal on the clock signal line and driven by which one of first and second modes of operation is designated to output one of first and second clock signals based on the internal clock signal, the first mode of operation allowing starting reading data from the semiconductor device one clock after a read command is applied when the external clock signal has a first transition for activation, the second mode of operation allowing starting reading data from the semiconductor device two clocks after the read command is applied when the external clock signal has the first transition for activation, the second clock signal in the second mode of operation being equal in frequency to the external clock and being synchronized with the external clock, the first clock signal in first mode of operation pulsing twice for activation within a period of the internal clock signal; a data bus transmitting data read from the memory cell array; an equalization circuit operative in response to an equalization signal to equalize the data bus; a command signal line transmitting the equalization signal from the control circuit; a data input/output terminal; and an input/output circuit outputting to the data input/output terminal the read data transmitted on the data bus, the input/output circuit including a latch circuit operative in the second mode of operation to store and hold the read data therein in response to the second clock signal attaining an active state, and operative in the first mode of operation to store and hold the read data therein in response to the first clock signal and the equalization signal each attaining an active state.
Preferably, the memory cell array includes a plurality of bit lines each provided to correspond to the column of memory cells to transmit data from a corresponding memory cell, a plurality of sense amplifiers enabled by a sense amplifier enable signal to amplify a potential of the bit line, and a column select circuit enabled by a column select enable signal to select the column of memory cells selected in response to an external address signal, and the control circuit activates the column select enable signal in response to one of external read and write commands being applied the sense amplifier enable signal also having an active state.
Thus the present invention has a main advantage that in both of a first mode of operation allowing starting reading data one clock after a read command is applied when an external clock signal has a first transition for activation and a second mode of operation allowing starting reading data two clocks after the read command is applied when the external clock signal has the first transition for activation, the device can output data, as timed without delay, and also avoid having a further increased circuit area.
The present invention has another advantage that the device can output data, as timed without delay, if an external dock signal has a period larger than its design specification.